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19th Euromicro Conference on Digital System Design (DSD 2016)

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From: "HR-Net News Distribution Manager" <>

Originally From: George Angelos Papadopoulos <george at>

*** First Call for Papers ***

19th Euromicro Conference on Digital System Design (DSD 2016)

Aug. 31st - Sept. 2nd, 2016, St. Raphael Resort, Limassol, Cyprus

Collocated with the 42nd Euromicro Conference on Software Engineering and Advanced Applications (SEAA 2016)


The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed HW/SW system engineering, covering the whole design trajectory from specification down to micro-architectures, digital circuits and VLSI implementations. It is a forum for researchers and engineers from academia and industry working on advanced investigations, developments and applications.

It focuses on today's and future challenges of advanced system architectures for embedded and high-performance HW/SW systems, application analysis and parallelization, design automation for all design levels, as well as, on modern implementation technologies from full custom in nanometer technology nodes, through FPGAs, to multi-core infrastructures. It covers a multitude of highly relevant design aspects from system, hardware and  embedded-software specification, modeling, analysis, synthesis and validation, through system adaptability, security, dependability and fault  tolerance, to system energy consumption minimization and multi-objective optimization.

Authors are kindly invited to submit their work according (but not limited)  to the seven main topics of the conference main track. In addition, eight Special Sessions (with their own coordinators and subprogram committees)  do also welcome contributions in specific themes of particular interest.  All papers are reviewed following guidelines, quality requirements and thresholds that are common to all committees.


T1: Advanced applications of embedded and cyber-physical systems

Challenging and highly-demanding modern applications in (wireless) communication and networking; networked electronic media, multimedia and ambient intelligence; image and video processing; mobile systems; ubiquitous, wearable and implanted systems; military, space, avionics, measurement, control and automotive applications; wireless sensor network applications; surveillance and security; environmental, agriculture, urban, building, transportation, traffic, energy, hazard and disaster monitoring and control.

T2: Application analysis and parallelization for embedded and high- performance hardware and software design

Application profiling, characterization and bottleneck detection; application restructuring for parallelism; application parallelization, information-flow analysis, scheduling and mapping for application-specific processor; MPSoC memory and communication architecture synthesis; HW/SW co-design and algorithm/architecture matching; combined hardware/software design space exploration and HW/SW system multi-objective optimization; parallelization, scheduling and mapping of applications for (heterogeneous) processor and MPSoC architectures; re-targetable (application-specific) compilation; architectural support for compilers/programming models; performance,  energy consumption and other parametric analysis for HW/SW systems; analytical modeling and simulation tools; benchmark applications, workload and benchmarking for heterogeneous HW/SW systems; virtual and FPGA-based system prototyping.

T3: Specification, modeling, analysis, verification and test for systems, hardware and embedded software 

Modeling, simulation, design and verification languages; functional, structural and parametric specification and modeling; model-based design and verification; system, hardware, and embedded software analysis, simulation, emulation, prototyping, formal verification, design-for-test and testing at all design levels; dependability, safety, security and fault-tolerance issues. 

T4: Design and synthesis of systems, hardware and embedded software 

Quality-driven design; model-, platform- and template-based design; design-space exploration; multi-objective optimization; system, processor, memory and communication architecture design; application scheduling and mapping to platforms; (Heterogeneous) multiprocessor systems on-a-chip (MPSoC), hardware multiprocessors and complex accelerators; generic system platforms and platform-based design; processor, memory and communication architectures; 3D MPSoCs and 3D NoCs; ASIP- and GPU-based platforms; software design and programming models for multicore platforms; IP design, standardization and reuse; parallelism exploitation and scalability techniques; virtual components; system of systems; compiler assisted MPSoCs; hardware support for embedded kernels; embedded software features; static, run-time and dynamic optimizations of embedded MPSoCs; benchmarks and benchmarking for MPSoCs; NoC architecture and quality of service; power dissipation and energy issues in SoCs and NoCs.

T6: Programmable/reconfigurable/adaptable architectures

Design methodologies and tools for reconfigurable computing; run-time,  partial and dynamic reconfiguration; fine-grained, mixed-grained and coarse-grained reconfigurable architectures; reconfigurable interconnections and NoCs; FPGAs; systems on reconfigurable chip; system FPGAs, structured ASICs; co-processors; processing arrays; programmable fabrics; adaptive computing devices, systems and software; adaptable ASIPs and ASIP-based MPSoCs; hardware accelerators; optimization of FPGA-based cores; shared resource management; novel models, design algorithms and tools for FPGAs and FPGA-based systems; rapid prototyping systems and platforms; adaptable wireless and mobile systems.

T7: New issues introduced by emerging technologies

Important issues for system, circuit and embedded software design introduced by e.g. the nanometer CMOS and beyond CMOS technologies, 3D integration, optical and other new memory and communication technologies; new human-machine interfaces; neural- and bio-computation; (bio) sensor and sensor network technologies; pervasive and ubiquitous computing (Internet of Things); related design methods and EDA tools; Flexible Digital Radio-digital architecture design and methodologies concepts for multi-standard, multi-mode flexible radios.


DTFT: Dependability, Testing and Fault Tolerance in Digital Systems H. Kubatova (CTU Prague, CZ), Z. Kotasek (TU Brno, CZ)

MCSDIA: Mixed Criticality System Design, Implementation and Analysis K. Gruttner (OFFIS, DE), E. Villar (TEISA U Cantabria, ES)

AHSA: Architectures and Hardware for Security Applications Paris Kitsos (TEI of Western Greece, GR)

DCPS: Design of Heterogeneous Cyber-Physical Systems M. Geilen, (TUE, NL), D. Quaglia (U Verona, IT)

ASHWPA: Advanced Systems in Healthcare, Wellness and Personal Assistance F. Leporati (U Pavia, IT)

ASAIT: Architectures and Systems for Automotive and Intelligent Transportation S. Niar (U Valenciennes, FR)

SDSG: System Design for the Smart Grid R. Jacobsen (Aarhus U, DK), E. Ebeid (Aarhus U, DK)

EPDSD: European Projects in Digital System Design F. Leporati (U Pavia, IT), L. Jozwiak (TUE, NL)


Authors are encouraged to submit their manuscripts to  Should an unexpected web access problem be encountered, please contact the Program Chair by email (

Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the IEEE format: single-spaced, double column, US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors' names should appear in the manuscript, references included.

CPS, Conference Publishing Services, publishes the (ISI indexed) DSD Proceedings, available worldwide through the IEEE Xplore Digital Library. Extended versions of selected best papers will be published in a special issue of the ISI indexed "Microprocessors and Microsystems: Embedded Hardware Design" Elsevier journal


· Submission of papers: April 8, 2016

· Notification of acceptance/rejection: May 30, 2016

· Camera-Ready submission: June 27, 2016


· Lech Jozwiak (TU Eindhoven, NL) - Chairman

· Krzysztof Kuchcinski (U Lund, SE)

· Antonio Nunez (IUMA/ULPGC, ES)

· Francesco Leporati (U Pavia, IT)

· Eugenio Villar (TEISA U Cantabria, ES)

· Jose Silva Matos (U Porto, PT)


· Paris Kitsos (TEI West. Greece, GR) - Chair

· Odysseas Koufopavlou (U Patras, GR) - Honorary Chair


· George A. Papadopoulos (U Cyprus, CY)

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